1. Field of the Invention
The present invention relates to a driving device, a column electrode driving semiconductor integrated circuit and a row electrode driving semiconductor integrated circuit which are used mainly for driving a liquid crystal display element.
2. Discussion of Background
FIG. 7 is a block diagram showing schematically the construction of a conventional liquid crystal display device. In FIG. 7, a liquid crystal panel 20 for displaying pictures has a number of super-twisted nematic (STN) liquid crystal display elements which are arranged in a matrix form so as to correspond to pixels. In the vicinity of the liquid crystal panel 20, there are arranged row drivers (Y drivers) 22 formed of a semiconductor integrated circuit (a large scale integrated circuit, hereinbelow, referred to as a LSI) which drives scanning lines and column drivers (X drivers) 21 formed of a LSI which outputs display data to the display panel 20.
As shown in FIG. 7, a plural number of column drivers 21 and row drivers 22 are generally used in order to drive a large number of scanning lines to thereby output a large number of a display data. Each of the column drivers 21 includes a latch circuit to latch display data on selection lines and a selection circuit to select applied voltages. Each of the row drivers 22 includes a shift register to shift a signal indicating a selection line and a selection circuit to select a voltage applied to a scanning line. In a case of using a monochrome VGA panel comprising X=640 dots and Y=480 dots for instance, four column drivers 21 and four row drivers 22 are used. In this case, each of the row drivers 22 takes charge of a 480/4=120 number of outputs 27. Namely, it outputs 120 selection signals. Further, each of the column drivers 21 takes charge of a 640.times.4=160 number of outputs 28. Namely, each of the column drivers 22 applies voltage levels necessary for an ON/OFF display to the liquid crystal panel 21 through the 160 number of outputs 28.
A controller 23 is to write input display data in a RAM 24 once and to supply control signals to the column drivers 21 and the row drivers 22 through control signal lines 25, 26. When a dot matrix type liquid crystal display device is used, address signals and read/write signals are supplied from the controller 23 to the RAM 24 to read or write display data. When a plurality of display RAMs 24 are provided, chip select signals are supplied from the controller 23 to the display RAMS.
Control signals to be supplied from the controller 23 to the column drivers 21 include display data, clocks for taking the display data, enable signals for activating the column drivers, latch pulses for outputting data to the liquid crystal panel 20, voltages for liquid crystal display to be applied to the liquid crystal panel 20 by means of the column drivers and signals for transforming liquid crystal driving outputs into an alternating current form.
Control signals supplied from the controller 23 to the row drivers 22 include selection data (shift data), shift clocks for shifting the selection data, voltages for liquid crystal display to be applied to the liquid crystal display panel 20 by means of the row drivers and signals for transforming liquid crystal display outputs into an alternating current form.
As described above, the liquid crystal display device, in particular, the liquid crystal display apparatus having a large-sized liquid crystal panel 20, requires a large number of control signals, a large number of drivers 21, 22, memories having a large capacity and the controller 23 of a large scale.
In a case of using the liquid crystal panel 20 for color display, 3 dots for R, G and B colors are required for a pixel. For instance, in a display panel comprising 640.times.480 pixels, a 640.times.3.times.480 number of liquid crystal display elements are required. Accordingly, the quantity of data to be treated is three times, and the number of the column drivers 21 is three times as much as the case of a monochrome display. Thus, the construction of the circuit in such a color liquid crystal display device is complicated and large.
In the above-mentioned liquid crystal display device, a scanning line is selected at a time. Recently, however, there has been developed methods wherein the liquid crystal display device is driven by selecting a plurality of scanning lines at a time. In the driving methods, there is a method of selecting the entire lines at a time as disclosed in the publication of EP 507061. Further, there is a method of dividing all the scanning lines into several groups and selecting the lines in each group at a time, as disclosed in U.S. Pat. No. 5,262,881. FIG. 8 is a block diagram showing the construction of a driving circuit for the liquid crystal display device which is suitable for these methods.
In FIG. 8, A-D converters 31R, 31G and 31B are adapted to convert R, G and B data to be displayed into digital data. A corrector 32 is to store each of the digital data to a display RAM 24 after the digital data are subjected to a .gamma.-correction or the like. A data selector 34 reads out data from the display RAM 24 in accordance with a predetermined algorithm so that the data are stored in memories 35a-35n. Gray shade control circuits 36a-36n read data from the memories 35a-35n to conduct a gray shade control to the data. An arithmetic circuit 37 performs predetermined arithmetic operations to row selection patterns and the outputs of the gray shade control circuits 36a-36n to produce display data to be outputted to the liquid crystal panel 20 and supplies the display data to the column drivers 21. A timing generating circuit 40 supplies timing signals to the A-D converters 31R, 31G, 31B and a row data generating circuit 41. The row data generating circuit 41 supplies simultaneous selection patterns to the row drivers 22. A delay circuit 42 delays the simultaneous selection patterns so that the simultaneous selection patterns to be supplied to the row drivers 22 are in synchronism with display data to be supplied to the column drivers 21.
In FIG. 8, the data selector 34, the arithmetic circuit 37, the timing generating circuit 40, the row data generating circuit 41 and the delay circuit 42 correspond to the controller 23 shown in FIG. 7. Also, the corrector 32, the memories 35a-35n and the gray shade control circuits 36a-36n can be included in the controller 23. For simplifying, a single column driver 21 and a single row driver 22 are shown in FIG. 8.
The operation of the liquid crystal panel 21 will be described in more detail. The A-D converters 31R, 31G, 31B are supposed to have a 6-bit output respectively. Namely, the converters convert R, G and B data as analogue signals into digital data of 64 grades of gray shade in accordance with the timing signals from the timing generating circuit 40. The corrector 32 performs a correction treatment such as a .gamma.-correction or the like to each of the digital data, and performs a bit conversion to a requisite number of bits, for instance, 3 bits (8 gray shades). Namely, the 6 bit data are transformed into 3 bit data when the data are corrected to have a linear form with respect to the brightness and the data values of the liquid crystal panel 20. The data after the correction are stored in the display RAM 24.
When the number of the simultaneous selection lines is 7, the number of groups in 480 lines is 480/7=68.57.apprxeq.69. In this case, the number of memories 35a-35n to be provided is 69. The data selector 34 distributes the data of 7 lines.times.640.times.3 bits which are for the groups, to the memories 35a-35n. Accordingly, in each of the memories 35a-35n, data of (simultaneously selected 7 lines).times.640.times.3, i.e. data corresponding to the display area of each group (7.times.640) of pixels are set. The data of R, G and B are of 3 bits respectively. Namely, there are 7.times.640.times.3 bits for R, G and B to each of the display areas. The gray shade control circuits 36a-36n conduct a gray shade control according to a frame modulation method or a dithering method. For instance, when the frame modulation as shown in FIG. 9 is to be conducted, it is necessary to set data for a plurality of frames in each of the memories 35a-35n. Then, each of the memories 35a-35n should have a capacity of several times as large as 7.times.640.times.3 bits. Each of the gray shade control circuits 36a-36n converts 3 bit data for each R, G, B into 1 bit data for each R, G, B according to the frame modulation or the dithering method. Accordingly, each information of 7.times.640 bits are successively outputted to the display areas of each R, G, B from the gray shade control circuits 36a-36n.
The arithmetic circuit 37 has such a construction as shown in FIG. 10 for instance. It receives selection data as 7-bit simultaneously selected row selection patterns. FIG. 10 shows a case that [0101010] are inputted as the selection data. The arithmetic circuit 37 receives data on the group to be driven firstly wherein the data are of a 7 row 1 column data (7 bits) when the data of 7.times.640 are considered as a matrix of 7.times.640. Each exclusive OR circuit 80 calculates the exclusive OR of the data and the selection data for each bit. Then, four full adders 81 calculate the results obtained by the exclusive OR circuits to obtain an arithmetic sum. The value as a result of the arithmetic sum takes any value of 0 through 7. Accordingly, the results of processing can be expressed by 3 bits. This treatment is executed for each R, G, B. The results of processing 3 bits for R, G, B are supplied to the column drivers 21. Then, the arithmetic circuit 37 conducts the above-mentioned treatment on a 7 row 2 column data, and the result of processing is supplied to the column drivers 21. In the same manner as above, of 7 low m column data (m represents numbers up to 640) are successively processed as described above.
When the treatment of the group to be driven firstly comprising 7 rows and 640 columns is finished, the arithmetic circuit 37 conducts the above-mentioned treatment for the group to be driven next. When the treatment is finished for all the groups, the treatment of 1 frame is finished.
FIG. 11 is a block diagram showing an example of the construction of the column driver 21. The column driver 21 is constituted by a single LSI. In FIG. 11, a data memory 50 stores display data on 64 columns. A shift register 51 is to shift seed signals for writing (start pulses) to designate address locations in the data memory 50. A display latch 53 latches the data in the data memory 50 to supply them to a liquid crystal driving circuit 58 when latch signals (LS) are inputted. A control circuit 52 supplies control signals to the data memory 50, the shift register 51 and the display latch 53. Assuming that the column driver 21 treats the display data on 64 columns, 10 column drivers 21 are needed in order to drive the display panel 20 having 640 pixels per row. The 10 column drivers 21 are cascadedly connected. Namely, an output of the shift register 51 is inputted to the shift register 51 in the column driver of the next stage. Thus, display data from the arithmetic circuit 37 are supplied to the data memory 50 in all the column drivers 21.
The operation of the column driver 21 shown in FIG. 11 will be described. When the control circuit 52 receives an EIO1 signal, it activates the data memory 50, the shift register 51 and the display latch 53. The data memory 50 receives from the arithmetic circuit 37 signals indicative of display data of 3 bits per column for R, G and B, i.e. 9 bits in total. The shift register 51 shifts the start pulses, and the data on 64 stages of the shift register 51 are supplied as addressing signals 54 to the data memory 50. Accordingly, the display data of each of the columns are successively stored at different addressing locations in the data memory 50. When the control circuit 52 confirms that the data on 64 columns have been written in the data memory 50, it outputs an EIO2 signal to the column driver 21 of the next stage. The next stage column driver 21 receives the EIO2 signal from the former stage, as the EIO1 signal.
The column driver 21 of the next stage, when it has received the EIO1 signal, takes the display data on 64 columns by performing the same operation as the column driver 21 of the former stage. Latch signals are inputted to the column drivers at the same timing of the inputting of the display data to the column drivers 21. Then, the display data stored in the data memory 50 in each of the column drivers 21 are latched by the display latch 53, whereby the display data of 640.times.3 dots are supplied to ten liquid crystal driving circuits 58.
Each of the display data is composed of 3 bits. Each of the liquid crystal driving circuits 58 includes a decoder and a level shifter. Further, voltages of 8 levels V0-V7 are inputted to the liquid crystal driving circuit 58, and the circuit 58 decodes the data of 3 bits per dot from the display latch 53. Also, the liquid crystal driving circuit 58 selects voltages corresponding to decoded values and applies the voltages to the liquid crystal display elements. A single liquid crystal driving circuit 58 produces a 3 (for each dot for R, G and B).times.64 (which correspond to the number of pixels)=192 number of outputs to the liquid crystal display panel 20. Accordingly, the liquid crystal display panel 20 receives a 192.times.10=1,920 number of outputs. Each of the outputs assumes any voltage value among the voltages V0-V7.
The above-mentioned description concerns a case of using the column drivers 21 to a STN color liquid crystal panel. However, column drivers for a TFT (thin film transistor) liquid crystal panel can be used for the column drivers 21. Further, the memory 50 and the shift register 51 may be replaced by shift registers for R, B and B.
FIG. 12 is a block diagram showing an embodiment of the construction of each of the row drivers 22. The row driver 22 is constituted by a single LSI. In FIG. 12, a shift register 70 shifts data SPDI (selection data) by shift clocks DSCK. A selection pattern register 72 takes the selection data in response to load signals LOAD. A shift register 74 shifts frame pulses by using the load signals LOAD as shift clocks. A liquid crystal driving circuit 75 applies the selection data set in the selection pattern register 72 to the row electrodes.
The operation of the row driver 22 will be described in more detail in a case that the selection pattern shown in FIG. 13 in which a multiplex line simultaneous selection method as disclosed in U.S. Pat. No. 5,262,881 is used.
Supposing that the row driver 22 shown in FIG. 12 produces 84 outputs, it is necessary to provide a 480/84.apprxeq.6 number of row drivers 22 when a liquid crystal display device having 480 scanning lines is used. The row drivers are cascadedly connected. Since the number of row electrodes simultaneously selected is 7, 84 row electrodes are divided into 84/7=12 groups.
For instance, when the selection data on the second column indicated by a dotted circle line "a" in FIG. 13 are serially inputted as the data SPDI to the shift register 70, the shift register 70 shifts the selection ata by the shift clocks DSCK. After 7 shift clocks DSCK have been inputted, load signals LOAD are received. Then, the selection pattern register 72 takes the content of the shift register 70. Accordingly, the selection data composed of parallel signals are set in the selection pattern register 72.
The shift register 74 is of a register having 12 stages. When the row driver 22 is of the first stage in 6 row drivers, frame pulses indicating the top of a frame are inputted as an input IOL, whereby the frame pulses are shifted by using the load signals LOAD as shift clocks. The content of the shift register 74 is supplied as signals for selecting the groups to the liquid crystal driving circuit 75. Further, voltages V.sup.+ and V.sup.- to be used at the selection time and a voltage VG (an intermediate voltage between V.sup.+ and V.sup.-) to be used at the non-selection time are supplied to the liquid crystal driving circuit 75. The liquid crystal driving circuit 75 detects a selected group by decoding inputted signals of the data of the shift register 74. In a case that the first group is selected, the liquid crystal driving circuit 75 supplies voltages in response to the number of bits corresponding to the content of the selection pattern register 72, to 7 row electrodes included in the first group. Namely, a level shift circuit in the liquid crystal driving circuit 75 applies the selection voltage V.sup.+ when the corresponding bit is "1", and the selection voltage V.sup.- when the corresponding bit is "0". Each of the row electrodes in the non-selected eleven groups is applied with the non-selection voltage VG. At this moment, the column driver 21 applies to each column electrode the voltages corresponding to the display data which correspond to the selected row electrodes in the same manner as the operation described above.
Then, outputs supplied from the selection pattern register 72 to the liquid crystal driving circuit 75 are successively changed, and selection voltages are applied to each row electrode of each group. When the selection of the groups has been finished for all 12 groups, the frame pulses are forced out as the output IOR of the shift register 74, and the frame pulses are supplied as an input IOL to the row driver 22 of the next stage. The row driver 22 of the next stage performs the same processing as above. Thus, the selection voltages are applied to each of the groups.
Since the conventional liquid crystal driving circuit driven by a multiple line simultaneous selection method has the above-mentioned construction, it has problems as follows.
The display RAM 24 is required as an essential element because there is a difference between the speed of inputted data and the speed of outputted data to the liquid crystal panel 20, and the difference should be absorbed. Generally, data to be inputted are successively fed from the first scanning line to the following scanning lines. In the multiple line simultaneous selection method, however, calculations on column electrodes have to be conducted. Namely, it is necessary to treat simultaneously the display data on the same column in a several number of selection lines. Accordingly, it is necessary to store the data in memories.
Further, memories 35a-35n are needed in addition to the display RAM 24. In an attempt to use only the memories 35a-35n while the display RAM 24 is eliminated, the control of addressing wherein the data on the scanning lines successively supplied have to be rearranged to write them in the memories 35a-35n is complicated, and a large-scaled address control circuit has to be provided.
A commercially available video RAM (V-RAM) can be used for the display RAM 24 and the memories 35a-35n because it can write in and read out data simultaneously. In the video RAM, however, all the memory regions are not always used, and a waste region may be produced.
In the arithmetic circuit 37 to which the multiple line simultaneous selection method is applied, a high speed of arithmetic calculation is required. For instance, in a case that a display of 40 frames per second is required and 7 lines have to be simultaneously selected for a liquid crystal panel 20 of 640.times.(R, G, B).times.480 dots, the speed of arithmetic operation per dot is: EQU 1(SEC)/40(F).times.(7(L)/480(D))/640=569.66 nsec.
When the selection pattern shown in FIG. 13 is used, the pattern has to be in an alternating current form, and it is necessary to perform arithmetic calculations for all the columns (8 columns) for the selection pattern. As a result, the calculations for each column have to be at a speed of EQU 569.66/8=71.2 nsec.
Actually, a further large number of frames have to be supplied to the liquid crystal panel 20 for each second in order to display a dynamic picture such as a driven car or the like. Accordingly, the arithmetic circuit 37 is required to have a further high speed of operation and a transferring speed for the column driver 21.
In order to increase the speed of calculations, a clock signal having a high frequency is required, whereby a power consumption rate is increased from a formula: EQU P=IV=fCV.multidot.V.
Further, since a large number of memories 35a-35n having a relatively large capacity are provided for the calculation of the row voltages, the consumption of power is increased. This means that it is difficult to use a driving circuit for the multiple line simultaneous selection method in a small sized portable device.
Further, as described above, since the conventional driving circuit for realizing the multiple line simultaneous selection method inevitably has a large scale and a large number of parts, it is difficult to use it for small-sized portable devices.